The present invention relates to a bus system for signal transmission and a memory system using the same and more particularly, to a bus system having a bus for coupling a plurality of integrated circuits formed on a printed wiring board.
In recent years, higher performance has been desired in an information processing apparatus such as a personal computer. In order to realize the higher performance, not only performance of a processor for performing the operation process is required to be improved but also transfer throughput of a bus adapted to couple integrated circuits and LSI's (hereinafter referred to as modules) should be improved.
As measures to improve the throughput, either a method of widening the bit width of the bus or a method of increasing the operating frequency of the bus has been available. With a recent tendency toward miniaturization of apparatus, the former method is however difficult to materialize and in general, the latter method has been adopted. As a technique corresponding to the latter method, a low amplitude bus interface utilizing a low signal amplitude of about 1V, such as a GTL (Gunning Transistor Logic) disclosed in, for example, U.S Pat. No. 5,023,488, has been used widely.
In a conventional bus using a TTL (Transistor Transistor Logic), the operating frequency is limited to about 66 MHz but in the low amplitude bus interface such as the GTL, operation even at frequencies amounting up to 100 MHz or more can be permitted.
On the other hand, with the semiconductor fabrication techniques promoted, fineness of the semiconductor internal structure has been accelerated and the operating speed of semiconductors have been increasing. Accordingly, rise time and fall time of a signal are decreased and in signal transmission on the bus, distortion of a signal waveform tends to increase.
Measures to decrease the waveform distortion as above have been taken, including a method in which matching termination is effected at both ends of the bus based on the aforementioned GTL interface, a SSTL (Stub Series Terminated Logic) method disclosed in JP-A-8-286793 and a dumping resistor method applicable to the conventional TTL.
For example, the prior art low amplitude bus system is comprised of modules 100, 110 and 120 and bus parts 201 to 204, as shown in FIG. 6. The modules 100, 110 and 120 are respectively integrated circuits having GTL interfaces.
In the modules 100, 110 and 120, the individual interface circuits include input circuits in the form of comparators 101, 111 and 121, output circuits in the form of MOS transistors 103, 113 and 123, and capacitors 102, 112 and 122 representative of equivalent capacitive components of the input circuits (here, comparators 101, 111 and 121).
Assumptively, in the prior art construction as above, each of the bus parts 201 to 204 has the same characteristic impedance Z0 and terminating resistors 301 and 302 have each a resistance equal to the characteristic impedance Z0 under the direction of matching termination which minimizes reflection from the bus end. The bus takes a wiring form of single stroke wiring starting with the terminating resistor 301, going through the modules 100, 110 and 120 and ending in the terminating resistor 302.
As an example of operation of the bus system shown in FIG. 6, data transfer from module 100 to module 110 will be described. Voltage wave forms occurring at junction nodes V1, V2 and V3 on the bus in FIG. 6 during the data transfer from module 100 to module 110 are simulated to obtain results as exemplified in FIG. 7.
At time t1, voltage at the junction node V1 of the module 100 becomes high level and a change of voltage from low level to high level propagates on the bus part 202 from the module 100 to the module 110. Subsequently, at time t2, voltage at the junction node V2 of the module 110 becomes high level.
At time t3 following a propagation delay time of the bus part 203, a change of voltage from low level to high level reaches the junction node V3 of the module 120. When the voltage change reaches the junction node V3 at the time t3, part of the voltage change is reflected and returned by the capacitor 122 representative of the equivalent input capacitive component of the module 120, producing a valley-like waveform distortion 901 in the voltage waveform at the node point V2 at time t4 (t3-t2=t4-t3).
As shown in FIG. 6, in the module 110 (modules 100 and 120 likewise), the input circuit in the form of the comparator 111 compares a threshold voltage Vth, which is a predetermined DC voltage, with the voltage at the junction node V2. Then, if the voltage at the junction node V2 is higher than the threshold voltage Vth, data of "1" is recognized but if lower, data of "0" is recognized.
Pursuant to general characteristics of the comparator 111, the voltage at the junction node V2 of the module 110 cannot sometimes be recognized correctly in a range covering the close proximity to the threshold voltage Vth. This range is called a blind zone which is designated by 801 in FIG. 7. Thus, even when the module 110 tries to fetch the voltage at the junction node V2 near the time t4, a voltage Vp1 associated with the waveform distortion 901 comes at the blind zone 801 and recognition of data "1" cannot always be warranted.
As described above, even in the matching termination bus such as the GTL interface, the waveform is distorted under the influence of the reflection by the capacitive component owned by the module and correct data transfer is sometimes prevented. This problem is raise by the steep rise time and fall time of output signals concomitant with the fineness of semiconductors and the promoted operating frequency of the bus and has not hitherto surfaced.
One method of solving the aforementioned problem is given by the SSTL interface disclosed in JP-A-8-286793. The SSTL interface, however, presupposes a push-pull type (low/high drive is effected by a pMOS transistor and an nMOS transistor) interface and cannot be applied to an open drain type (only the low side is driven by an nMOS transistor) interface which can be of wired OR connection. Another method of inserting a dumping resistor has hitherto been known and is applicable to the TTL interface. Essentially, however, this conventional method intends to control the output end impedance in unidirectional transmission and its application to the bidirectional bus is difficult to achieve.